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Based on ELMEC’s expertise in producing High-speed Delay Lines, the FDG-type mid-speed SIP Fixed Delay Line reduces the number of internal elements by 1/3 to 1/2.
By reducing the number of elements, the Passband will narrow by approx 1/2 compared to the FDC/FDD-types, however, it is also possible to make a comparable reduction in price. If your clock adjustment is within 1/2 of a cycle, the FDG-type should suffice for your needs. It is a RoHS-compliant component. The terminals are Nickel with a Tin plating. |
| Impedance: |
FDG1E205 : 50W±10%
Other Parts : 100W±10%
Components can be designed at 200W up to 25ns, and 500W up to 10ns. If you are concerned about low power consumption and looking for a higher-impedance Delay Line, please let us know. |
| Waveform Distortion: |
Overshoot/preshoot under ±20% |
| Temperature Coefficient: |
-50 to +200ppm/°C |
| Insulation Resistance: |
DC50V, over 100MW |
| Durable Voltage: |
DC50V, 1 minute |
| Operating Temperature Range: |
-40°C to +85°C |
| Storage Temperature Range: |
-40°C to +120°C |
Unit:mm(inch)
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Soldering Conditions
Flow Solder 260°C, under 10 seconds
Soldering Iron 350°C, under 5 seconds |
Product Specifications
| Part Number |
Delay Time |
Rise Time
(20-80% Max) |
-3 dB
Passband
(Guarantee) |
DC
Resistance |
Simulation
Model
and Data |
| FDG1010 |
1ns ±0.2ns |
0.6ns Max |
DC~600MHz |
1.0Ω Max |
E S T |
| FDG2010 |
2ns ±0.2ns |
0.6ns Max |
DC~600MHz |
1.0Ω Max |
E S T |
| FDG3010 |
3ns ±0.3ns |
0.9ns Max |
DC~400MHz |
1.0Ω Max |
E S T |
| FDG4010 |
4ns ±0.3ns |
1.2ns Max |
DC~300MHz |
1.0Ω Max |
E S T |
| FDG5010 |
5ns ±0.4ns |
1.4ns Max |
DC~250MHz |
1.5Ω Max |
E S T |
| FDG6010 |
6ns ±0.5ns |
1.8ns Max |
DC~200MHz |
1.5Ω Max |
E S T |
| FDG7010 |
7ns ±0.5ns |
2.0ns Max |
DC~180MHz |
1.5Ω Max |
E S T |
| FDG8010 |
8ns ±0.6ns |
2.4ns Max |
DC~150MHz |
2.0Ω Max |
E S T |
| FDG9010 |
9ns ±0.7ns |
2.5ns Max |
DC~140MHz |
2.0Ω Max |
E S T |
| FDG10010 |
10ns ±0.7ns |
3.0ns Max |
DC~120MHz |
2.0Ω Max |
E S T |
| FDG12010 |
12ns ±0.9ns |
3.5ns Max |
DC~100MHz |
2.5Ω Max |
E S T |
| FDG13010 |
13ns ±1.0ns |
3.7ns Max |
DC~95MHz |
2.5Ω Max |
E S T |
| FDG15010 |
15ns ±1.1ns |
4.2ns Max |
DC~85MHz |
2.5Ω Max |
E S T |
| FDG16010 |
16ns ±1.2ns |
4.4ns Max |
DC~80MHz |
3.0Ω Max |
E S T |
| FDG18010 |
18ns ±1.3ns |
5.0ns Max |
DC~70MHz |
4.0Ω Max |
E S T |
| FDG20010 |
20ns ±1.4ns |
5.5ns Max |
DC~65MHz |
4.5Ω Max |
E S T |
| FDG22010 |
22ns ±1.6ns |
5.5ns Max |
DC~65MHz |
4.5Ω Max |
E S T |
| FDG25010 |
25ns ±1.8ns |
7.0ns Max |
DC~50MHz |
10.0Ω Max |
E S T |
| FDG30010 |
30ns ±2.1ns |
9.0ns Max |
DC~40MHz |
15.0Ω Max |
E S T |
| FDG35010 |
35ns ±2.5ns |
10.0ns Max |
DC~35MHz |
17.0Ω Max |
E S T |
| FDG40010 |
40ns ±2.8ns |
12.0ns Max |
DC~30MHz |
18.0Ω Max |
E S T |
| FDG45010 |
45ns ±3.2ns |
14.0ns Max |
DC~25MHz |
19.0Ω Max |
E S T |
| FDG50010 |
50ns ±3.5ns |
18.0ns Max |
DC~20MHz |
21.0Ω Max |
E S T |
| FDG1E205 |
100ns ±7.0ns |
35.0ns Max |
DC~10MHz |
21.0Ω Max |
E S T |
E - Uses Excel macro to indicate S-parameter, Group Delay characteristics, Pulse Response Wave.
S - SPICE Model
T - Touchstone format (S2P file) |
(1) Analog circuit
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r: Signal Source Impedance
Rin: Input Adjustment Resistance
Zo: Characteristic Impedance
r+Rin=Zo=R |
(2) ECL (-2V termination line used)
 Connect to one of the VCC, VEE or -2V lines
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(3) ECL (-2V termination line not used)(PECL)
Connect to either VCC or VEE lines
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(4) LVPECL
Connect to either 3.3V or GND
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(5) TTL(FAST),CMOS(FACT)
Ro should be adjusted to a value near Zo.
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FDG10010
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Output waveform
(Step function)
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Amplitude / Frequency
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Output waveform
(50MHz Clock)
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Group Delay
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FDG20010
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Output waveform
(Step function)
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Amplitude / Frequency
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Output waveform
(25MHz Clock)
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Group Delay
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FDG50010
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Output waveform
(Step function)
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Amplitude / Frequency
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Output waveform
(10MHz Clock)
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Group Delay
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1. Compliance Status
Initially developed only as a RoHS-compliant component.
2. Terminal Plating
Base: 100% Ni
External: 100% Sn
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